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NX2710
SINGLE CHANNEL PWM CONTROLLER WITH NMOS LDO CONTROLLER AND 5V BIAS REGULATOR
ADVANCE DATA SHEET Pb Free Product
DESCRIPTION
The NX2710 controller IC is a compact synchronous Buck controller IC with 16 lead SOIC package designed for step down DC to DC converter applications with feedforward functionality. Voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. The NX2710 controller is optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the regulator off until the supply voltage exceeds 9V where internal digital soft starts get initiated to ramp up output. The NX2710 employs programmable current limiting and FB UVLO followed by HICCUP feature. Other features include: 5V gate drive, Programmable frequency from 300kHz to 1MHz, Adaptive deadband control, Internal digital soft start; Vcc under voltage lockout and shutdown capability via comp pin.
n n n n n n n n n n n n n n
FEATURES
Bus voltage operation from 9V to 24V 5V bias regulator available Excellent dynamic response with input voltage feed-forward and voltage mode control Programmable switching frequency up to 1MHz Internal Digital Soft Start Function Programmable hiccup current limit Shutdown by pulling COMP pin low NMOS LDO controller available Start into precharged output Pb-free and RoHS compliant Notebook PC Graphic Card on board converters On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display
APPLICATIONS
TYPICAL APPLICATION
DO3316P-102 MBR0530T1 8 VIN BST HDRV 9 1 0.1uF 2 Q1 0.75uH REGCS SW 16 OCP 12 REGOUT VCC 8.06k 3.3nF Q2 1.2k 2.5k 7.5k 2*16SVP330M
VIN1 +12V
1uF 1ohm
VOUT1 +1.2V@25A
2*(560uF,7mohm)
NX2710
10
LDRV 4 GND Fb Comp 3 14 15
+5V
10uF 5k 1uF
13
15nF 15k
680pF
11 1.65k
REGFB
VIN2 +3.3V
5 RT
LDO OUT
6 82pF 5k 0 5k
MTD3055
LDO FB 7
150uF 18mohm
VOUT2 +1.6V@2A
Figure1 - Typical application of NX2710
ORDERING INFORMATION
Device NX2710CSTR
Rev. 1.3 08/07/07
Temperature 0 to 70o C
Package SOIC -16L
Frequency 300kHz to 1MHz
Pb-Free Yes 1
NX2710
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V VIN to GND .......................................................... -0.3V to 25V BST, HDRV, REGCS to GND Voltage .................. -0.3V to 35V SW to GND ......................................................... -2V to 35V REGOUT to GND ................................................. 0.2 to 16V All other pins ....................................................... -0.3V to 6.5V Storage Temperature Range ................................. -65oC to 150oC Operating Junction Temperature Range ................ -40oC to 125oC ESD Susceptibility .............................................. 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
16-LEAD PLASTIC SOIC
JA 83o C/W
BST HDRV GND LDRV RT LDO-OUT LDO-FB VIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SW COMP FB VCC OCP REGSEN REGOUT REGCS
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = 0 to 70oC. Typical values refer to TA = 25oC.
PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range Operating quiescent current Vcc UVLO VCC-Threshold VCC-Hysteresis Supply Voltage(Vin) Vin Voltage Range Input Voltage Current SYM VREF Test Condition Min TYP 0.8 0.2 4.75 switching is off 3 4.4 0.2 9 Vin=24V 9 25 10 5.25 5 MAX Units V % V mA V V V mA
VCC IQ
VCC_UVLO VCC Rising VCC_Hyst VCC Falling Vin
Rev. 1.3 08/07/07
2
NX2710
PARAMETER Vin UVLO Vin-Threshold Vin-Hysteresis Oscillator (Rt) Frequency Frequency Over Vin Ramp-Amplitude Voltage Ramp Offset Ramp/Vin Gain Max Duty Cycle Min on time Error Amplifiers Transconductance Input Bias Current Comp SD threshold Vref and Soft Start Soft Start time High Side Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low N Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time OCP Adjust OCP current setting FBUVLO Feedback UVLO threshold Over temperature Threshold Hysteresis
Rev. 1.3 08/07/07
SYM Vin_UVLO Vin_Hyst FS VRAMP
Test Condition Vin Rising Vin Falling RT=open
Min
TYP 8.8 0.8 300
MAX
Units V V KHz % V V V/V % nS umho nA V mS
-5 Vin=20V 2 0.8 0.1 90
5
150 2500 Ib 0.3 Tss Fs=300kHz 6.8 100
Rsource(Hdrv) Rsink(Hdrv)
I=200mA I=200mA
1 0.8 50 50 30
ohm ohm ns ns ns
THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10%
Rsource(Ldrv) Rsink(Ldrv)
I=200mA I=200mA
1 0.5 50 50 30
ohm ohm ns ns ns
TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10%
32 percent of nominal 65 70 150 20 75
uA % C C 3
NX2710
PARAMETER LDO Controller FB Pin- Bias Current LDO FB Voltage LDO FB UVLO High Output Voltage Low Output Voltage High Output Source Current 5V AUX REG Current limit threshold FB Pin- Bias Current RegFb Voltage Regout Output Voltage High Regout Output Voltage Low Open Loop Gain SYM Test Condition Min TYP MAX 100 LDO_OUT=LDO_FB percent of nominal VIN=12V, LDO_FB=0.7V IO_SOURCE=1.4mA VIN=12V, LDO_FB=0.9V IO_SINK=1.4mA 65 0.8 70 10.2 0.2 3 100 0 1.25 11 0.2 50 75 Units nA V % V V mA mV uA V V V DB
Regout=RegFb VIN=12V, RegFb=1.1V IO_SOURCE=1.4mA VIN=12V, IO_SINK=1.4mA GBNT(Note1) RegFb=1.4V
Note 1: This parameter is guaranteed by design but not tested in production(GBNT).
Rev. 1.3 08/07/07
4
NX2710
PIN DESCRIPTIONS
PIN SYMBOL VCC PIN DESCRIPTION This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. Power ground. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage.
BST GND
FB
COMP
This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is connected to source of high side FETs and provide return path for the high side driver. High side gate driver output. Low side gate driver output. Bus voltage input provides power supply to oscillator, VIN UVLO signal and 5V regulator controller.
SW HDRV LDRV VIN
RT
Oscillator's frequency can be set by using an external resistor from this pin to GND. LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP circuitry. LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. This pin is 5V regulator current limit pin. It compares the voltage drop on the resistor which is connected between Vin and REGCS pin with internal offset 100mV. 1ohm resistor sets the current limit 100mA. The output of the 5V regulator controller that drives a low current low cost external bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived from bus voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. Feedback pin of the 5V regulator controller. A resistor divider is connected from the output of the 5V regulator to this pin to complete the loop. This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. 5
LDO FB
LDO OUT
REGCS
REGOUT
REGSEN
OCP
Rev. 1.3 08/07/07
NX2710
BLOCK DIAGRAM
RegCs VIN Ref
+
Regout
100mV Regsen VCC 4.4/4.2 Bias 1.25V Generator 0.8V 6/5.75 COMP 0.3V three cycle delay Hiccup START Reset dominant R S EN POR BST START START DrvH
Q
LDIN
SW
START Digital start Up RT
VIN SS_1/4_done OSC Dis_EA SS_half_done S R Q 3 cycle filter
FET Drivers HDin
VCC
DRVL Disable SS_done
70%*Vp FB
Vp
Vp
POR Hiccup R Hiccup logic 0.6V CLAMP
HDIN
FB
3 cycle filter 32uA LDIN START VCC
OCP
COMP Dis_EA GND EN
0.6V SS_1/4_done 3 cycle filter VpLDO Vp LDO_out 70%*Vp
LDO_FB
Figure 2 - Simplified block diagram of the NX2710
Rev. 1.3 08/07/07
6
NX2710
DO3316P-102 MBR0530T1 8 VIN BST HDRV 9 1 0.1uF 1ohm 2 Q1 0.75uH REGCS SW 16 OCP 12 2N3904 REGOUT VCC 6k 3.3nF Q2 1.2k 2.5k 7.5k 2* 10uF
16MV1500WG
VIN1 +12V
1uF
VOUT1 +1.2V@25A
2*(560uF,7mohm)
NX2710
5k
10 10 1uF 13
LDRV 4 GND Fb Comp 3 14 15
+5V
1uF 5k
15nF 15k
680pF
11 1.65k
REGFB 100uF 6 150pF 470 1k 220uF 39mohm
VIN2 +3.3V
5 RT
LDO OUT
MTD3055
LDO FB 7
VOUT2 +2.5V@2A
Figure 3 - Simplified Demo board schematic
Rev. 1.3 08/07/07
7
NX2710
R23 0 MH1 R24 0 J1 1 L3 DO3316H-102 R29 1 C20 op C21 1u C25 0.1u D1 MBR0530T1 R22 0 BST 1 VCC 2 C12 VDD C11 16MV1500WG open C9 10u R25 4.99k R26 op C7 op VCC C26 1u R27 5k R28 1.65k SW 11 REG_SENSE 16 C2 0.1u R34 op R12 0 R13 0 SW D5 op SW 1 L1 2 4SEPC560MX 4SEPC560MX op VOUT 2 C14 C15 C19 R18 1k GNDOUT LG1 M3 NTD110N02R VOUT UG2 NTD70N03R M2 C10 10u 8 5V 5V 3.3V 1 3.3V 2 3 4 5 6 7 8 9 12V 10 10 REG_OUT HDRV 2 HDRV UG1 M1 NTD70N03R 3.3V1 3.3V2 GND 5V1 GND1 5V GND2 PWR_OK 5VSB MH2 12V1 BUS 12V C18 47u 1 3.3V -12V GND3 PS_ON GND4 GND5 GND6 -5V 5V2 5V3 11 12 13 14 15 16 17 18 19 20 5V 5V R5 1k 1 2 J2 GND1 GND2 3.3V MH1 1
GND
MH1
MH1
12V1 12V2
4 12V 3 12V
U1 9 Q1 MBR3904 M6 op
REG_CS
V IN
MH2
MH2
ATX-12V
ATX con MH2 1
JVOUT
C17 0.1u
PG0077.801 1 L2
NX2710
OCP
12
R4 6k R14 0 R15 LD R V 0 R16 0 LG3 LG2
D2
D3
D4
OP
3.3V 3
R1 10
13 C1 1u
VCC
M4
JP1
2
LDO_IN C22 100u
R17 NTD110N02R 10 VDD 8 7 6 5 9 M5 C13 470p UG1 4 NTD110N02R 8 7 6 5 9
M7 6 LDO_OUT
LDRV
4
op
MTD3055 LDO_OUT LDO_OUT panasonic FM 220uF JLDO C23 1 2 3 4 5 R31 0 R33 1k C8 150p 7 R32 474 R30 op 5
M11 UG2 4
M12
FB LDO_FB GND RT COMP
14 C3 op 15 R3 open C5 680p C6 open C4 15n R2 1.2k 2.5k
R20 7.5k R19 C16 3.3n
1 2 3
SW
GNDLDO
C24 0.1u
SW 8 7 6 5 9 8 7 6 5 9 R21 15k LG1 4 8 7 6 5 9 op M15 LG3 4 1 2 3 op
3
M13 LG2 4
op
M14
1 2 3
NX2710 HC APPLICATION
Size Date: Document Number Rev
2710-SO-02A
Thursday , September 14, 2006 Sheet 1 of 1
A
Figure 4 - Demo board schematic based on ORCAD
Rev. 1.3 08/07/07
1 2 3
Title
1 2 3
op
VOUT
1
5 4 3 2
8
NX2710
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Quantity 3 4 1 1 1 2 1 1 2 1 1 1 1 1 1 1 2 3 1 1 2 1 1 3 9 1 1 1 1 1 1 1 1 1 Reference C1,C21,C26 C2,C17,C24,C25 C4 C5 C8 C9,C10 C11 C13 C14,C15 C16 C18 C22 C23 D1 L1 L3 M1,M2 M3,M4,M5 M7 Q1 R1,R17 R2 R4 R5,R18,R33 R12,R13,R14,R15,R16,R22, R23,R24,R31 R19 R20 R21 R25 R27 R28 R29 R32 U1 Part 1u 0.1u 15n 680p 150p 10u 16MV1500WG 470p 4SEPC560MX 3.3n 47u 100u panasonic FM 220uF MBR0530T1 PG0077.801 DO3316H-102 NTD70N03R NTD110N02R MTD3055 MBR3904 10 2.5k 6k 1k 0 1.2k 7.5k 15k 4.99k 5k 1.65k 1 474 NX2710
Rev. 1.3 08/07/07
9
NX2710
Demoboard waveforms
Figure 5 - Output ripple
Figure 6 -
Transient response @ 1.2 output
Figure 7 - Transient response @ LDO
Figure 8 - Soft start
Figure 9 - 1.2V over current proteciton
Rev. 1.3 08/07/07
Figure 10 - LDO over current protection 10
NX2710
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS DIRIPPLE - Input voltage - Output voltage - Output current - Switching frequency - Inductor current ripple
IRIPPLE = =
VIN -VOUT VOUT 1 x x LOUT VIN FS
...(2) 12V-1.2V 1.2V 1 x x = 4.8A 0.75uH 12V 300kHz
Output Capacitor Selection
Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3).
DVRIPPLE - Output voltage ripple
Design Example
Power stage design requirements: VIN=12V VOUT=1.2V IOUT =25A DVRIPPLE <=20mV DVTRAN<=60mV @ 10A step FS=300kHz
VRIPPLE = ESR x IRIPPLE +
IRIPPLE 8 x FS x COUT
...(3)
Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, OSCON are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
ESR desire =
VRIPPLE 15mV = = 4.2m IRIPPLE 4.8A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 15mV output ripple, OSCON 4SEPC560MX with 7m are chosen.
V -V V 1 L OUT = IN OUT x OUT x IRIPPLE VIN FS IRIPPLE =k x IOUTPUT
where k is between 0.2 to 0.4. Select k=0.2, then
...(1)
N=
E S R E x IR I P P L E VR IPPLE
7m x 4.8A 20mV
...(5)
LOUT =
12V-1.2V 1.2V 1 x x 0.2 x 25A 12V 300kHz LOUT =0.72uH
Number of Capacitor is calculated as
N=
Choose LOUT=0.75uH, then Pulse inductor PG0077.801 is a good choice. Current Ripple is calculated as
Rev. 1.3 08/07/07
N =1.68 The number of capacitor has to be round up to a integer. Choose N =2. 11
NX2710
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. capacitor output ripple is : The amount of ceramic output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is mostly like to dependent on the ESR of capacitor. Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
VRIPPLE = ESR x IRIPPLE
IRIPPLE + 8 x 300kHz x COUT
Using the above equations, although DC ripple spec can be met, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as V droop < V tran @step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation.
...(9)
where
0 if L L crit = L x Istep - ESR E x CE V OUT
if
L L crit
...(10)
For example, assume voltage droop during transient is 60mV for 10A load step. If the OSCON 4SEPC560MX(560uF, 7mohm ESR) is used, the crticial inductance is given as
L crit =
ESR E x C E x VOUT = Istep
7m x 560F x1.2V = 0.94H 5A
The selected inductor is 0.75uH which is smaller than critical inductance. In that case, the output voltage transient mainly dependent on the ESR. number of capacitor is
Vovershoot
where
VOUT = ESR x Istep + x 2 2 x L x COUT
...(6)
is the a function of capacitor,etc.
L L crit
...(7)
0 if L L crit = L x Istep - ESR x COUT V OUT
where
L crit =
N=
ESR E x Istep Vtran
if
ESR x COUT x VOUT ESR E x C E x VOUT = ...(8) Istep I step
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected
7m x 5A 60mV = 1.296 The number of capacitors has to satisfied both ripple and transient requirement. Overall, we choose N=2. =
Rev. 1.3 08/07/07
12
NX2710
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. following figures and equations show how to realize the type III compensator by transconductance amplifier.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 2 x x R4 x C1 x C2 C1 + C2
...(11) ...(12) ...(13) ...(14)
Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. Voltage feedforward compensation is used in NX2710 to compensate the output voltage variation caused by input voltage changing. The feedforward funtion is realized by using VIN pin voltage to program the oscillator ramp voltage VOSC=0.1VIN, which provides nearly constant power stage gain under wide voltage input range.
where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by:
Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1
For the voltage amplifier, the transfer function of compensator is
Ve -Z f = VOUT Zin
To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time,
Zin R3
Vout
Zf C1 C2 Fb gm Ve R4
R2 C3 R1
A. Type III compensator design
For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The
Rev. 1.3 08/07/07
Vref
Figure 11 - Type III compensator using transconductance amplifier 13
NX2710
Case 1: FLCC2 =
1 2 x x FZ1 x R 4
Gain(db)
power stage
=
FLC
40dB/decade
1 2 x x 0.75 x 5.5kHz x 2.5k = 15nF
Choose C2=15nF. 4. Calculate C1 by equation (14) with pole Fp2 at one third of the switching frequency.
loop gain
FESR
20dB/decade compensator
C1
1 2 x x R 4 x FP2
1 x x 2.5k x 100kHz 2 639pF
Choose C1=680pF. 5. Calculate C3 with the crossover frequency FO at 15kHz.
FZ1 FZ2
FO FP1
FP2
C3 =
VOSC 2 x x FO x L x COUT x VIN R4
Figure 12 - Bode plot of Type III compensator (FLC1 2 x x 15kHz x 0.75uH x 1120uF x 10 2.5k =3.2nF =
Choose C3=3.3nF. 6. Calculate R3 by equation (13) with Fp1 =FESR.
R3 = =
1 2 x x FP1 x C3
1 2 x x 40.6kHz x 3.3nF = 1.18k
Choose R3 =1.2k. 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole.
FLC = =
1 2 x x LOUT x COUT 1
2 x x 0.75uH x 1120uF = 5.5kHz
R2 = =
1 1 1 x( - ) 2 x x C3 FZ2 FP1
FESR = =
1 2 x x ESR x COUT
1 2 x x 3.5m x 1120uF = 40.6kHz
1 1 1 x( - ) 2 x x 3.3nF 5.5kHz 40.6kHz = 7.6k
Choose R2 =7.5k. 8. Calculate R1
.
14
2. Set R4 equal to 2.5k.
Rev. 1.3 08/07/07
NX2710
R1 = R 2 x VREF 7.5k x 0.8V = = 15k VOUT -VREF 1.2V-0.8V
FLC = = 1 2 x x LOUT x COUT 1
Choose R 1=15k. Case 2: FLC2 x x 2.2uH x 2000uF = 2.4kHz
FESR =
1 2 x x ESR x COUT
Gain(db)
power stage
FLC
40dB/decade
1 2 x x 9m x 2000uF = 8.8kHz =
2. Set R4 equal to 2.5k. 3. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
FESR
loop gain
C2 =
1 2 x x FZ1 x R 4
20dB/decade compensator
=
1 2 x x 0.75 x 2.4kHz x 2.5k = 35nF
Choose C2=33nF. 4. Calculate C1 by equation (14) with pole Fp2 at one third of the switching frequency.
FZ1 FZ2 FP1 FO
FP2
C1
1 2 x x R 4 x FP2
Figure 13 - Bode plot of Type III compensator (FLC1 2 x x 2.5k x 66.7kHz 959pF
Choose C1=1nF. 5. Calculate R3 with the crossover frequency FO at 15kHz.
R3 =
VIN ESR x R 4 x VOSC 2 x x FO x L
9mohm x 2.5k 2 x x 15kHz x 1uH =1.08k =10 x
Choose R3=1.2k. 6. Calculate C3 by equation (13) with Fp1 =FESR.
Rev. 1.3 08/07/07
15
NX2710
Gain(db)
C3 = =
1 2 x x FP1 x R3
power stage 40dB/decade loop gain 20dB/decade
1 2 x x 8.8kHz x 1.2k = 14nF
Choose C3 =15nF. 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole.
R2 = =
1 1 1 x( - ) 2 x x C3 FZ2 FP1
compensator Gain
1 1 1 x( - ) 2 x x 15nF 2.4kHz 8.8kHz = 3.2k
Choose R2 =4k. 8. Calculate R1
FZ FLC FESR FO FP
Figure 14 - Bode plot of Type II compensator
.
R1 =
R 2 x VREF 7.5k x 0.8V = = 15k VOUT -VREF 1.2V-0.8V
Choose R 1=15k.
Vout R2 Fb gm R1 Vref Ve R3 C2 C1
B. Type II compensator design
If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. For this type of compensator, FO need to satisfy FLCFigure 15 - Type II compensator with transconductance amplifier The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V, output inductor is 2.2uH, output capacitors are
Gain=gm x Fz =
R1 x R3 R1 +R 2
... (15) ... (16) ... (17)
1 2 x x R3 x C1 1 2 x x R 3 x C2
t 680uF wih 41m electrolytic capacitors. wo t
1.Calculate the location of LC double pole FLC and ESR zero FESR.
Fp
FLC = =
1 2 x x L OUT x COUT 1
2 x x 2.2uH x 1360uF = 2.9kHz
Rev. 1.3 08/07/07
16
NX2710
FESR = = 1 2 x x ESR x COUT
The following equation applies to figure16, which shows the relationship between age divider.
VOUT , VREF and volt-
1 2 x x 20.5m x 1360uF = 5.7kHz
2.Set R2 equal to10k. Using equation 18, the final selection of R1 is 4.7k. 3. Set crossover frequency at 1/10 of the swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation.
Vout R2 Fb R1 Vref
R3 =
VOSC 2 x x FO x L 1 VOUT x x x Vin RESR gm VREF
Figure 16 - Voltage Divider
=0.1x
2 x x 30kHz x 2.2uH 1 x 20.5m 2.5mA/V 2.5V x 0.8V =2.53k
R 1=
R 2 x VR E F V O U T -V R E F
...(18)
where R2 is part of the compensator, and the value of R1 value can be set by voltage divider.
Choose R3 =2.55k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as:
1 C1 = 2 x x R3 x Fz = 1 2 x x 2.55k x 0.75 x 2.9kHz =28nF
Choose C1=27nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency.
C2= 1 x R 3 x Fs
IRMS = IOUT x D x 1- D D= VOUT VIN
...(19)
1 = x 2 .55k x 300kH z =207pF
Choose C2=220pF.
VIN = 12V, VOUT=1.2V, IOUT=25A, the result of input RMS current is 7.5A. For higher efficiency, low ESR capacitors are recommended. Two Sanyo OS-CON 16SVP330M
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value.
Rev. 1.3 08/07/07
16V 330uF 16m with 4.72A RMS rating are chosen
as input capacitors.
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NX2710
Power MOSFETs Selection
The NX2710 requires at least two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In 25A output application, five IRFR3706 can be used, two for high side, three for low side. They have the following parameters: VDS=30V, ID =75A,RDSON =9m,QGATE =23nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as: charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device.
Over Current Limit Protection
Over current protection is achieved by sensing current through the low side MOSFET. An internal current source of 32uA flows through an external resistor connected from OCP pin to SW node sets the over current protection threshold. When synchronous FET is on, the voltage at node SW is given as
VSW =-IL x RDSON
The voltage at pin OCP is given as
PHCON =IOUT 2 x D x RDS(ON) x K PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
...(20)
IOCP x ROCP +VSW
When the voltage is below zero, the over current occurss as shown in figure 17.
vbus I OCP 32uA
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125 C according to IRFR3706 datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated.
o
OCP R OCP
SW
OCP comparator
Figure 17 - Over Current Protection The over current limit can be set by the following equation:
1 x VIN x IOUT x TSW x FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: PSW =
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
ISET =
IOCP x ROCP K x RDSON
If two MOSFETs RDSON=6.5m, the worst case thermal consideration K=1.5 and the current limit is set at 40A, then
R OCP = ISET x K x R DSON 40A x 1.5 x 6.5m = = 6.1k IOCP 32uA x 2
Choose ROCP=6k. For NX2710, if switching channel goes into hiccup current limit, the LDO will go to hiccup too.
LDO Selection Guide
NX2710 offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. The selection is that the Rdson of MOSFET should
...(22)
where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate
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NX2710
meet the dropout requirement. For example. VLDOIN =3.3V VLDOOUT =2.5V ILoad =2A The maximum Rdson of MOSFET should be
R RDSON = (VLDOIN - VLDOOUT ) x I LOAD = (3.3V - 2.5V) / 2A = 0.4
gm is the forward trans-conductance of MOSFET. For IRF3706, gm=53. Select Rf1=5kohm. Output capacitor is Sanyo POSCAP 4TPE150M with 150uF, ESR=25mohm.
CC = 1 53 x 25m x =91pF 4 x x 100kHz x 5k 1+53 x 25m
Most of MOSFETs can meet the requirement. Moreimportant is that MOSFET has to be selected right package to handle the thermal capability. For LDO, maximum power dissipation is given as
PLOSS = (VLDOIN - VLDOOUT ) x I LOAD = (3.3V - 2.5V) x 2A = 1.6W
Choose CC=100pF. For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage. R f2 = = R f1 x VREF VLDOOUT - VREF
Select IR MOSFET IRFR3706 with 9m RDSON is sufficient.
5k x 0.8V 1.6V - 0.8V =5k Choose Rf2=5k. When ceramic capacitors or some low ESR bulk capacitors are chosen as LDO output capacitors, the zero caused by output capacitor ESR is so high that crossover frequency FO has to be chosen much higher than zero caused by RC and CC and much lower than zero caused by ESR . For example, 10uF ceramic is used as output capacitor. We select Fo=100kHz, Rf1=5kohm and select MOSFET MTD3055(gm=5S).
LDO Compensation
The diagram of LDO controller including VCC regulator is shown in the following figure.
LDO input Vref Rf1 Rf2 Rc Cc Co ESR
+
Rload
RC and CC can be calculated as follows.
RC =R f1 x
2 x x FO x CO 0.5 x gm
Figure 18 - NX2710 LDO controller. For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows.
2 x x 100kHz x 10uF 0.5 x 5S =12.56k =5k x
Choose RC=12.7k.
CC =
10 x CO RC x gm
g x ESR 1 CC = xm 4 x x FO x R f1 1+gm x ESR
where FO is the desired crossover frequency. Typically, in this LDO compensation, crossover frequency FO has to be higher than zero caused by ESR. FO is typically around several tens kHz to a few hundred kHz. For this example, we select Fo=100kHz.
Rev. 1.3 08/07/07
10 x 10uF 12.7k x 5S =1 .6nF =
Choose CC=1.5nF.
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NX2710
Current Limit for LDO
Current limit of LDO is achieved by sensing the LDO feedback voltage. When LDO_FB pin is below 70% of VREF, the IC goes into hiccup mode. The IC will turn off all the channel for 4096 cycles and start to restart system again. enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function.
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
Rev. 1.3 08/07/07
need to be practi-
cally touching the drain pin of the upper MOSFET, a
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NX2710
SOIC16 PACKAGE OUTLINE DIMENSIONS
Rev. 1.3 08/07/07
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NX2710
Rev. 1.3 08/07/07
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NX2710
Customer Service NEXSEM Inc. 500 Wald Irvine, CA 92618 U.S.A. Tel: (949)453-0714 Fax: (949)453-0713 WWW.NEXSEM.COM
Rev. 1.3 08/07/07
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